The present invention relates to a semiconductor integrated circuit that is less affected by performance degradation of transistors with time, and also relates to a method for designing such a circuit.
Recent dramatic downsizing of semiconductor integrated circuits have caused various problems. As for transistors, a latch-up phenomenon and hot carrier effects are typical examples of those problems encountered often.
The hot carrier effects refer to a phenomenon in which greatly energetic electrons (which are also called xe2x80x9chot electronsxe2x80x9d) cross the junction of a semiconductor to enter the gate oxide of a transistor. After having entered the gate oxide, those hot electrons are trapped and accumulated in the oxide, thus increasing the threshold voltage of the transistor. As a result, the drivability of the current decreases. The longer the cumulative operation time of a transistor, the more degraded the transistor and the lower its operating speed become due to the hot carrier effects.
This degradation phenomenon is possibly retarded either by weakening the electric field within the channel or by reducing the current flowing through the transistor. In general, as a transistor is downsized, the supply voltage tends to decrease. However, since the effective channel length Leff also becomes shorter correspondingly, the electric field within the channel does not always weaken. Also, it would not be advantageous either to reduce the current flowing through the transistor. This is because the drivability of the transistor and the performance of an LSI, including that transistor, would both decline.
For further details of physical phenomena like these, see xe2x80x9cCircuits, Interconnections and Packaging for VLSIxe2x80x9d, Addison-Wesley Publishing Company, Inc.
In the prior art, the performance degradation of a transistor due to hot carrier effects has been estimated on a transistor-by-transistor basis. For example, transistors with degraded performance are spotted by incorporating a hot carrier effect degradation model into a circuit simulator (see, e.g., Japanese Laid-Open Publication No. 1-94484). According to another technique, the stress dependence of indices in a degradation rate equation is obtained, thereby simulating degradation due to the hot carrier effects under an AC stress (see, e.g., Japanese Laid-Open Publication No. 7-99302).
In the currently available timing simulation technique for logic circuits, the logic circuits are tested on the assumption that the performance of the logic circuits would not degrade with time. Actually, though, the transistors do degrade due to the hot carrier effects, and therefore, degradation of the logic circuits is also unavoidable. For example, delays of the logic circuits increase with time.
Particularly when a logic circuit on a critical path degrades after a long-time use, the performance of the entire circuit cannot be ensured even if proper operation thereof is ensured in its initial state. Thus, logic circuits should also be designed while taking future degradation thereof into account.
In addition, a degraded logic circuit also causes a problem in delivering a clock signal. In recent years, a gated clocking technique is often adopted for an LSI to reduce the power dissipation thereof. That is to say, where just a part of an LSI has to be operated, if a clock signal is delivered to the other unneeded part of the LSI, power is wasted by the clock delivery circuit in vain. Thus, according to the gated clocking technique, the clock delivery circuit is provided with a circuit for selectively delivering the clock signal to only the necessary part of an LSI.
FIG. 16(a) illustrates a conventional technique of delivering a clock signal. As shown in FIG. 16(a), a clock signal is always delivered from a clock signal source to both circuits A and B. In this case, the signal delivered to the circuits A and B changes its level the same number of times and therefore both of these circuits A and B degrade to the same degree. Thus, even after these circuits A and B have degraded with time, the clock skew between internal clock signals for the circuits A and B does not increase.
FIG. 16(b) illustrates a gated clocking technique. An AND circuit 73 is inserted as a clock controller between a circuit for delivering a clock signal to the circuit A and the circuit A. In response to a control signal input, the AND circuit 73 may stop delivering the clock signal to the circuit A. At a point in time, the total numbers of times the clock signal delivered to the circuits A and B has changed its level may be 1014 and 1016, respectively. In such a situation, the circuit B degrades at a higher rate and causes a longer delay than the circuit A. As a result, the clock skew between the internal clock signals for the circuits A and B increases after these circuits have degraded with time.
Furthermore, a clock net is generally implemented as a clock tree, in which degradation rates are also variable among the clock controllers for respective branches. Accordingly, after a long time has passed, the clock skew may also increase for that reason.
It is therefore an object of the present invention to provide (1) a semiconductor integrated circuit that is less affected by performance degradation with time by implementing transistors in such a configuration as suppressing the degradation due to hot carrier effects, and (2) a method for designing such a circuit.
Specifically, an inventive semiconductor integrated circuit includes a complementary metal oxide semiconductor (CMOS) logic circuit with multiple input terminals. The CMOS logic circuit includes a plurality of serial connections of n-channel transistors. The serial connections are connected in parallel to each other between an output terminal and a ground line. In every one of the serial connections, each said input terminal is connected to the gate of at least one of the n-channel transistors. And in at least one of the serial connections, the input terminal is connected to the gate of one of the n-channel transistors that is more distant from the output terminal than another one of the n-channel transistors that is closest to the output terminal is.
According to the present invention, none of the input terminals of the CMOS logic circuit is connected to ONLY the n-channel transistors that are closest to the output terminal and most likely to degrade. Thus, there is no path in which a delay from the input terminal to the output terminal changes significantly due to degradation of the transistors.
In one embodiment of the present invention, each said input terminal is connected to the gate of one of the n-channel transistors in every one of the serial connections so as to minimize a maximum sum of degradation rates of the n-channel transistors that are connected to the same input terminal.
In such an embodiment, it is possible to average the rates of increase in delay time caused by the paths from respective input terminals to the output terminal due to degradation with time. Thus, none of the paths increases the delay time outstandingly.
An inventive logical design method for a semiconductor integrated circuit includes the steps of: a) generating a circuit at a logical level so as to meet given functions and specifications; b) extracting a critical path, which will cause the longest delay, from the circuit generated in the step a); c) counting how many times a path leading from each input terminal to an output terminal in every logic cell of the circuit has operated; d) calculating a degradation rate associated with the path leading from each said input terminal to the output terminal in each said logic cell on the critical path by reference to the number of times of operation obtained in the step c); and e) exchanging a connection to one of the input terminals of each said logic cell, which terminal is associated with the critical path, with a connection to another one of the input terminals of the logic cell, which terminal is associated with another path corresponding to a lower degradation rate than that of the critical path, by reference to the degradation rates obtained in the step d).
According to the inventive design method, it is possible to reduce the increase in delay due to degradation on the critical path, thus suppressing degradation of the overall circuit with time.
In one embodiment of the present invention, the degradation rates are obtained in the step d) using a delay library in which data about the degradation rates associated with multiple paths leading from the respective input terminals to the output terminal of each said logic cell is stored.
In such an embodiment, the degradation rate data stored in the delay library can be referred to in the design process. Thus, a circuit can be designed in view of the degradation of the circuit with time without performing simulations on the degradation.
Another inventive logical design method for a semiconductor integrated circuit uses a delay library in which data about a multi-input logic cell, including a plurality of input terminals, is stored. The data is so described as to obtain representative ranking of degradation rates associated with multiple paths between respective input terminals and an output terminal of the multi-input logic cell without specifying operating conditions for the paths.
According to the inventive method, a circuit can be designed easily in view of its degradation with time and without taking the difference in operating conditions (e.g., number of times of operation) among the respective path into account.
In one embodiment of the present invention, the data represents ranking of the degradation rates associated with the respective paths in the same logic cell.
In such an embodiment, the ranking of degradation rates associated with respective path in each logic cell can be known immediately.
In another embodiment of the present invention, the logical design method includes the steps of: a) generating a circuit at a logical level so as to meet given functions and specifications; b) extracting a critical path, which will cause the longest delay, from the circuit generated in the step a); c) selecting the multi-input logic cell from logic cells on the critical path; and d) exchanging a connection to one of the input terminals of the multi-input logic cell selected in the step c), which terminal is associated with the critical path, with a connection to another one of the input terminals of the logic cell, which terminal is associated with another path corresponding to a lower degradation rate than that of the critical path, by reference to the data stored in the delay library.
In such an embodiment, increase in delay on the critical path due to degradation with time can be suppressed without taking the difference in operating conditions (e.g., number of times of operation) into account.
In still another embodiment, an output of a logic cell implemented as a single-stage transistor is provided to one of the input terminals of the multi-input logic cell by reference to the data stored in the delay library. The terminal provided with the output is associated with one of the paths of the logic cell other than another one of its paths that corresponds to the highest degradation rate.
In such an embodiment, degradation with time can be suppressed in a logic cell next to a logic cell with a single-stage transistor structure.
In still another embodiment, the logical design method includes the steps of: a) generating a circuit at a logical level so as to meet given functions and specifications; b) obtaining switching probabilities of signals provided to the respective input terminals of the multi-input logic cell in the circuit; and c) modifying connections such that one of the signals with the highest switching probability is provided to one of the input terminals of the multi-input logic cell by reference to the data stored in the delay library. The input terminal provided with the signal is associated with one of the paths of the logic cell other than another one of its paths that corresponds to the highest degradation rate.
In such an embodiment, the number of times a path, which is most likely to degrade with time, has to operate can be reduced in the logic cell. Thus, increase in delay on that path can be suppressed.
In still another embodiment, an output of a sequential logic circuit operating synchronously with a clock signal is provided to one of the input terminals of the multi-input logic cell by reference to the data stored in the delay library. The terminal provided with the output is associated with one of the paths of the logic cell other than another one of its paths that corresponds to the highest degradation rate.
In such an embodiment, the number of times a path, which is most likely to degrade with time, has to operate can be reduced in the logic cell, to which the output of the sequential logic circuit is provided. Thus, increase in delay on that path can be suppressed.
In still another embodiment, if an output of a sequential logic circuit operating synchronously with a clock signal is provided to a single-input logic cell, the single-input logic cell is replaced with the multi-input logic cell. The output is provided to one of the input terminals of the multi-input logic cell by reference to the data stored in the delay library. The terminal provided with the output is associated with one of the paths of the logic cell other than another one of its paths that corresponds to the highest degradation rate.
In such an embodiment, a path of the multi-input logic cell that is least likely to degrade with time is operated instead of the single-input logic cell. Thus, increase in delay is avoidable with more certainty compared to the single-input logic cell.
Another inventive semiconductor integrated circuit includes an AND logic circuit with three or more input terminals and a serial connection of n-channel transistors. A clock signal is provided to a first one of the input terminals of the logic circuit. A signal controlling clock delivery is provided to a second one of the input terminals of the logic circuit. And a potential in logically high state is applied to the other input terminals of the logic circuit. The first input terminal is connected to the gate of one of the n-channel transistors in the serial connection. The n-channel transistor is more distant from the output terminal than another one of the n-channel transistors that is closest to the output terminal is.
In the inventive semiconductor integrated circuit, a clock signal, which changes its level frequently, is input to the gate of the transistor that is less likely to degrade. Thus, a circuit, which is less likely to degrade or increase its clock skew, is realized.
Still another inventive semiconductor integrated circuit also includes an AND logic circuit with three or more input terminals and a serial connection of n-channel transistors. A clock signal is provided to a first one of the input terminals of the logic circuit. A signal controlling clock delivery is provided to a second one of the input terminals of the logic circuit. And a potential in logically high state is applied to the other input terminals of the logic circuit. The first input terminal is connected to the gate of one of the n-channel transistors in the serial connection. The n-channel transistor is other than another one of the n-channel transistors that has the highest degradation rate.
In the inventive semiconductor integrated circuit, a clock signal is input to the gate of the transistor that is least likely to degrade. Thus, a circuit, which is less likely to degrade or increase its clock skew, is realized.
In an inventive method for designing a semiconductor integrated circuit, increase in signal propagation delay due to degradation of the circuit is suppressed by replacing an inverter with a NAND cell including two or more input terminals and a serial connection of n-channel transistors. An input terminal of the inverter is replaced with one of the input terminals of the NAND cell that is connected to the gate of one of the n-channel transistors in the serial connection. The n-channel transistor is more distant from an output terminal than another one of the n-channel transistors that is closest to the output terminal is. An output terminal of the inverter is replaced with an output terminal of the NAND cell. And a potential in logically high state is applied to the other input terminals of the NAND cell.
According to the inventive method, when a NAND cell is operated as an inverter, an input signal is provided to the gate of one of its transistors with the lowest degradation rate. Thus, the resulting circuit will degrade to a much lesser degree.